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1 of 24 050202 note: some revi sions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: htt p://www.maxim - ic.com/er rata . features generates and detects digital patterns for analyzing and trouble - shooting digital communications systems programmable polynomial length and feedback taps for generation of any pseudorandom patterns up to 2 32 - 1; up to 32 taps can be u sed in the feedback path programmable, user - defined pattern registers for long repetitive patterns up to 512 bytes in length large 48 - bit count and bit error count registers software - programmable bit error insertion fully independent transmit and receive p aths 8 - bit parallel - control port detects polynomial test patterns in the presence of bit error rates up to 10 - 2 programmable for serial, 4 - bit parallel, or 8 - bit parallel data interfaces serial mode clock rate is 155mhz; byte mode is 80mhz for a net 622mbp s; oc - 3 available in 44 - pin plcc ordering information DS2174Q 44 - pin plcc 0c to +70c DS2174Qn 44 - pin plcc - 40c to +85c pin assignment applications routers channel service units (csus) data service units (dsus) muxes switches digital - to - ana log converters (dacs) cpe equipment bridges smart jack description the ds2174 enhanced bit error rate tester (ebert) is a software - programmable test - pattern generator, receiver, and analyzer capable of meeting the most stringent error - performance requir ements of digital transmission facilities. it features bit - serial, nibble - parallel, and byte - parallel data interfaces, and generates and uniquely synchronizes to pseudorandom patterns of the form 2 n - 1, where n can take on values from 1 to 32, and user - de fined repetitive patterns of any length up to 512 octets. 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 d2 d1 d0 tdat7 tdat6 gnd tdat5 tdat4 tdat3 tdat2 gnd rdat3 rdat4 rdat5 rdat6 rdat7 gnd a0 a1 a2 a3 cs rdat2 rdat1 rdat0 rclk_en rclk vdd d7 d6 d5 d4 d3 rd wr test test gnd vdd tclk tclk_en tclko tdat0 tdat1 www.maxim - ic.com ds2174 ebert ds2174
ds2174 2 of 24 . table of contents 1. general operation ................................ ................................ ................................ ................ 4 1.1 pattern generation ................................ ................................ ................................ ........... 4 1.2 pattern synchronization ................................ ................................ ............................... 5 1.3 bit error rate (ber) calculation ................................ ................................ ............... 5 1.4 generating errors ................................ ................................ ................................ .............. 5 1.5 clock discussion ................................ ................................ ................................ .................. 6 1.6 power - up sequence ................................ ................................ ................................ .............. 6 1.7 detailed pin description ................................ ................................ ................................ .. 8 2. parallel control interface ................................ ................................ ........................ 10 3. control registers ................................ ................................ ................................ ............... 11 3.1 status register ................................ ................................ ................................ ................... 15 3.2 pseudorandom pattern registers ................................ ................................ ........... 15 3.3 test register ................................ ................................ ................................ ........................ 17 3.4 count registers ................................ ................................ ................................ .................. 17 4. ram access ................................ ................................ ................................ ................................ . 18 4.1 indirect addressi ng ................................ ................................ ................................ ......... 18 5. dc operation ................................ ................................ ................................ ............................ 19 6. ac timing characteristics ................................ ................................ ............................. 20 6.1 parallel port ................................ ................................ ................................ ...................... 20 6.2 data interface ................................ ................................ ................................ .................... 22 7. mechanical dimensions ................................ ................................ ................................ .... 24
ds2174 3 of 24 list of figures figure 1 - 1: block diagram ................................ ................................ ................................ ............. 6 figure 6 - 1: read timing ................................ ................................ ................................ .................. 20 figure 6 - 2: write timing ................................ ................................ ................................ ................ 21 figur e 6 - 3: transmit interface timing ................................ ................................ .................. 22 figure 6 - 4: receive interface timing ................................ ................................ ..................... 23 list of tables table 1 - 1: pin assignment ................................ ................................ ................................ ............... 7 table 2 - 1: register map ................................ ................................ ................................ ................. 10 table 3 - 1: mode select ................................ ................................ ................................ .................. 13 table 3 - 2: error bit insertion ................................ ................................ ................................ ... 13 t able 3 - 3: pseudorandom pattern generation ................................ ............................... 16 table 5 - 1: recommended dc operating conditions ................................ ....................... 19 table 5 - 2: dc characteristics ................................ ................................ ................................ ... 19 table 6 - 1: parallel port read timing ................................ ................................ ................... 20 table 6 - 2: parallel port write timing ................................ ................................ ................. 21 table 6 - 3: transmit data timing ................................ ................................ .............................. 22 table 6 - 4: r eceive data timing ................................ ................................ ................................ . 23
ds2174 4 of 24 1. general operation 1.1 pattern generation polynomial generation the ds2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path of the polynomial generator. it also features a seed register that can be used to preload the polynomial generator with a seed value. this is done on the rising edge of tl in control register 1. the ds2174 generates polynomial patterns of any length up to and including 2 32 - 1. all of the industry - standard polynomi als can be programmed using the control registers. the polynomial is generated using a shift register of programmable length and programmable feedback tap positions. the user has access to all combinations of pattern length and pattern tap location to gene rate industry - standard polynomials or other combinations as well. in addition, the qrss pattern described in t1.403 is described by the polynomial 2 20 - 1. this pattern has the additional requirement that ?an output bit is forced to a one whenever the next 14 bits are zero.? setting the qrss bit in control register 1 causes the pattern generator to enforce this rule. repetitive pattern generation in addition to polynomial patterns, the ds2174 generates repetitive patterns of considerable length. the progra mmer has access to 512 bytes of memory for storing pattern. the pattern length bits pl0 through pl8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. memory is addressed indirectly and is used to store the pattern . data can be sent msb or lsb first as it appears in the memory. repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to store patterns such as dds - n patterns or t1 - n patterns. repetitive patterns are stor ed in increments of 8 bits. to generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that the pattern is 24 bits long (3 bytes), and repeats twice in memory. the same is true when the device is used in serial mod e: a 5 - bit pattern is written to memory 5 times. for example, to generate a 00001 pattern at the serial output, write these bytes to memory: ram address binary code hex code 00h 00010000 10h 01h 01000010 42h 02h 00001000 08h 03h 00100001 21h 04h 100 00100 84h
ds2174 5 of 24 1.2 pattern synchronization synchronization the receiver synchronizes to the same pattern that is being transmitted. the pattern must be error free when the synchronizer is online. once synchronized, an error density of 6 bits in 64 causes t he receiver to declare loss of pattern sync, set the rlos bit, and the synchronizer comes back online. polynomial synchronization synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte mode), where n is the e xponent in the polynomial that describes the pattern. once synchronized, any bit that does not match the polynomial is counted as a bit error. repetitive pattern synchronization synchronization to repetitive patterns can take several complete repetitions of the entire pattern. the actual sync time depends on the nature of the pattern and the location of the synchronization pointer. errors that occur during synchronization could affect the sync time; at least one complete error - free repetition must be rece ived before synchronization is declared. once synchronized, any bit that does not match the pattern that is programmed in the on - board ram is counted as a bit error. 1.3 bit error rate (ber) calculation counters the bit counter is active at all times. o nce synchronized, the error counters come online. the receiver has large 48 - bit count registers. these counters accumulate for 50 , 640 hours at the t1 line rate, 1.544mhz, and 38 , 170 hours at the e1 line rate, 2.048mhz. at higher clock rates, the counters sat urate quicker, but at the t3 line rate, the counter still runs for almost 1500 hours, and at 155mhz it runs for 504 hours. to accumulate ber data, the user toggles the lc bit at t = 0. this clears the accumulators and loads the contents into the count reg isters. at t = 0, these results should be ignored. at this point, the device is counting bits and bit errors. at the end of the specified time interval, the user toggles the lc bit again and reads the count registers. these are the valid results used to ca lculate a bit error rate. remember, the bit counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied by 4 or 8 to get the correct bit count. for longer integration periods, the results of multiple read cyc les have to be accumulated in software. 1.4 generating errors through control register 2, the user can intentionally inject a particular error rate into the transmitted data stream. injecting errors allows users to stress communication links and to chec k the functionality of error monitoring equipment along the path.
ds2174 6 of 24 1.5 clock discussion there are two methods for moving test patterns through a telecom network. 1) the clock applied to tclk and rclk can be gapped by other devices on the target system. the gapped clock would be applied to tclk and rclk only during the appropriate times. tdatn outputs remain active during clock gaps. 2) the clock applied to tclk and rclk can be continuous at the applicable line rate and the tclk_en and rclk_en pins can be assert ed and deasserted during the appropriate time slots. tdatn outputs remain active even when tclk_en is pulled low. the output level remains static at the level of the last bit transmitted (output high for a 1, output low for a 0). 1.6 power - up sequence on power - up, the registers in the ds2174 are in a random state. the user must program all the internal registers to a known state before proper operation can be ensured. figure 1 - 1. block diagram bit counter error counter pattern detector error insertion loopback mux repetitive pattern generator 2 n - 1 parallel control port receive rate control transmit rate control d[7:0] cs rd wr a[3:0] rdat[7:0] tclk0 td at[7:0] tclk tclk_en rclk_en rclk sync cr1.5 lc cr1.0 tl
ds2174 7 of 24 table 1 - 1. pin assignment pin name i/o description 1 , 23 vdd ? supply 2 rclk i receive clock 3 rclk_en i receive clock enable 4 rdat0 i receive serial data or lsb of receive nibble or byte data 5 rdat1 i receive data nibble or byte 6 rdat2 i receive data nibble or byte 7 rdat3 i receive data nibble or byte 8 rdat4 i receive data byte 9 rdat5 i receive data byte 10 rdat6 i receive data byte 11 rdat7 i receive data byte 12 , 22, 29 , 34 gnd ? ground 13 a0 i address 0 14 a1 i address 1 15 a2 i address 2 16 a3 i address 3 17 cs i chip select 18 rd i read 19 wr i write 20 , 21 test i test input 24 tclk i transmit clock input 25 tclk_en i transmit clock enable 26 tclko o transmit clock output. this is active only when data is being transmitted. this clock has gapped periods corresponding to the times when the transmit enable signal is low. 27 tdat0 o transmit serial data or lsb of transmit nibble or byte data 28 tdat1 o transmit data nibble or byte 30 tdat2 o transmit data nibble or byte 31 tdat3 o transmit data nibble or byte 32 tdat4 o transmit data byte 33 tdat5 o transmit data byte 35 tdat6 o transmit data byte 36 tdat7 o transmit data byte 37 d0 i/o data i/o 38 d1 i/o dat a i/o 39 d2 i/o data i/o 40 d3 i/o data i/o 41 d4 i/o data i/o 42 d5 i/o data i/o 43 d6 i/o data i/o 44 d7 i/o data i/o
ds2174 8 of 24 1.7 detailed pin description signal name: rclk signal description: receive clock signal type: input receive clock input. up to a 155mhz clock to operate the receive circuit. input data at rdatn is sampled on the rising edge of rclk. signal name: rclk_en signal description: receive clock enable signal type: input gaps the rclk input to the receive circuit. signal name: rdat0 to rdat7 signal description: receive data inputs signal type: input rdat0. receive serial data/receive data bit 0 in nibble and byte mode rdat1. receive data bit 1 in nibble and byte mode rdat2. receive data bit 2 in nibble and byte mode rdat3. receive dat a bit 3 in nibble and byte mode rdat4. receive data bit 4 in byte mode rdat5. receive data bit 5 in byte mode rdat6. receive data bit 6 in byte mode rdat7. receive data bit 7 in byte mode signal name: a0 to a3 signal description: address i nputs signal typ e: input address bus for addressing the control registers. signal name: cs signal description: chip select signal type: input active - low signal. must be low to read or write to the part. signal name: rd signal description: read strobe signal type: input active - low signal. must be low to read from the part. signal name: wr signal description: write strobe signal type: input active - low signal. must be low to write to the part. signal name: test signal description: test input signal type: input (with int ernal 10k ? pullup) test input. should be left floating or held high.
ds2174 9 of 24 signal name: test signal description: test input signal type: input (with internal 10k ? pullup) test input. should be left floating or held high. signal name: tclk signal description: tra nsmit c lock signal type: input transmit clock input. up to a 155mhz clock to operate the transmit circuit. data is output at tdatn and is updated on the rising edge of tclk. signal name: tclk_en signal description: transmit clock enable signal type: inpu t gaps the tclk input to the transmit circuit. signal name: tclko signal description: tclk output signal type: output output of the tclk gapping circuit. gapped by tclk_en. signal name: tdat0 to tdat7 signal description: transmit data outputs signal ty pe: output tdat0. transmit serial data/receive data bit 0 in nibble and byte mode tdat1.transmit data bit 1 in nibble and byte mode tdat2. transmit data bit 2 in nibble and byte mode tdat3. transmit data bit 3 in nibble and byte mode tdat4. transmit data b it 4 in byte mode tdat5. transmit data bit 5 in byte mode tdat6. transmit data bit 6 in byte mode tdat7. transmit data bit 7 in byte mode signal name: d0 to d7 signal description: data i/o signal type: i/o parallel data pins.
ds2174 10 of 24 2. parallel control interf ace access to the registers is provided through a nonmultiplexed parallel port. the data bus is 8 bits wide; the address bus is 4 bits wide. control registers are accessed directly; memory for long repetitive patterns is accessed indirectly. rclk and tclk are used to update counters and for all rising edge bits in the register map (rsync, lc, tl, sbe). at slow clock rates, sufficient time must be allowed for these port operations. table 2 - 1. register map address r/w register name 0 0 r/w control register 1 01 r/w control register 2 02 r/w control register 3 03 r/w control register 4 04 r status register 05 r/w tap/seed register 0 06 r/w tap/seed register 1 07 r/w tap/seed register 2 08 r/w tap/seed register 3 09 r/w test reg ister 0a r count register 0 0b r count register 1 0c r count register 2 0d r count register 3 0e r count register 4 0f r count register 5
ds2174 11 of 24 3. control registers control register 1 (address = 0h) (msb) (lsb) synce rsync lc lpbk qrss ps lsb tl symbol description synce sync enable. 0 = auto resync enabled 1 = auto resync disabled rsync initiate manual resync process. a rising edge causes the device to go out of sync and begin resynchronization process. lc latch count registers. a rising edge c opies the bit count and bit error count accumulators to the appropriate registers. the accumulators are then cleared. lpbk transmit/receive loopback select. 0 = loopback disabled 1 = loopback enabled qrss zero suppression select. forces a 1 into the pat tern whenever the next 14 bit positions are all 0?s. should only be set when using the qrss pattern. 0 = disable 14 zero suppression 1 = enable 14 zero suppression per t1.403 ps pattern select. 0 = pseudorandom pattern 1 = repetitive pattern lsb lsb/msb . 0 = repetitive p attern data is transmitted/received msb first 1 = repetitive p attern data is transmitted/received lsb first tl transmit load. a rising edge causes the transmit shift register to be loaded with the seed value.
ds2174 12 of 24 control register 2 (ad dress = 1h) (msb) (lsb) mode1 mode0 tinv rinv sbe eir2 eir1 eir0 symbol description mode1 mode select bit 1. see table 3. mode0 mode select bit 0. see table 3. tinv transmit data inversion select. 0 = do not invert outbound data 1 = invert out bound data rinv receive data inversion select. 0 = do not invert inbound data 1 = invert inbound data sbe single bit error insert. a rising edge causes the device to insert a single error in the outbound data. must be cleared by the user. eir2 error in sert bit 2. see table 4. eir1 error insert bit 1. see table 4. eir0 error insert bit 0. see table 4.
ds2174 13 of 24 mode select the ds2174 is configured to operate in bit, nibble, or byte mode by using the mode1/mode0 bits in control register 2. table 3 - 1. mode select mode1 mode0 operation mode 0 0 bit 0 1 nibble 1 0 byte 1 1 invalid error insertion the ds2174 inserts bit errors at a particular rate by setting the error insertion bits in control register 2 (table 4). in addition, the d evice inserts errors on command by setting the sbe bit in control register 2. the bit that occurs after the rising edge of the sbe insert bit is inverted. in the case of the qrss pattern, this could result in a string of 0?s longer than 14 bits; the ds2174 delays the erred bit by 1 clock cycle. data in the nibble and byte modes is presented 4 or 8 bits at a time. when in nibble or byte mode and selecting 10 - 1 error rate, the device actually produces an error rate of 8 - 1 . when in byte mode and selecting an error rate of 10 - 2 , the device produces an error rate of 8 - 2 . table 3 - 2. error bit insertion eir2 eir1 eir0 error rate serial nibble byte 0 0 0 none 4 4 4 0 0 1 10 - 1 4 8 - 1 8 - 1 0 1 0 10 - 2 4 4 8 - 2 0 1 1 10 - 3 4 4 4 1 0 0 10 - 4 4 4 4 1 0 1 10 - 5 4 4 4 1 1 0 10 - 6 4 4 4 1 1 1 10 - 7 4 4 4
ds2174 14 of 24 control register 3 (address = 2h) (msb) (lsb) pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 symbol description pl7 pattern length bit 7. bit 7 of [8:0] end address of repetitive pattern data. pl6 pattern length bit 6. bit 6 of [8:0] end address of repetitive pattern data. pl5 pattern length bit 5. bit 5 of [8:0] end address of repetitive pattern data. pl4 pattern length bit 4. bit 4 of [8:0] end address of repetitive pattern data. pl3 pattern length bit 3. bit 3 of [8:0 ] end address of repetitive pattern data. pl2 pattern length bit 2. bit 2 of [8:0] end address of repetitive pattern data. pl1 pattern length bit 1. bit 1 of [8:0] end address of repetitive pattern data. pl0 pattern length bit 0. bit 0 of [8:0] end addr ess of repetitive pattern data. control register 4 (address = 3h) (msb) (lsb) test test clk_inv r/w ram count seed pl8 symbol description test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. clk_inv tclko invert. 0 = tclko polarity is normal 1 = tclko polarity is inverted r/w read/write select. this bit is used with the ram bit to read or write the ram. 0 = write to the ram 1 = read from the ram ram ram select. this bit should be set when repetitive pattern data is being loaded into the ram. see flowchart in section 4 for a description of this process. 0 = bert state machine has control of the ram 1 = parallel port has read and write access to the ram count select bit for registe rs ah ? fh. 0 = registers ah ? fh refer to bit count registers. 1 = registers ah ? fh refer to error count registers. seed select bit for registers 5h ? 8h. 0 = registers 5h ? 8h refer to tap select registers. 1 = registers 5h ? 8h refer to preload seed registers. p l8 pattern length bit 8. bit 8 of [8:0] end address of repetitive pattern data.
ds2174 15 of 24 3.1 status register the status register contains information about the real - time status of the ds2174. when a particular event has occurred, the appropriate bit in the regi ster is set to a 1. all of the bits in this register (except for sync) operate in a latched fashion, which means that if an event occurs and a bit is set to a 1, it remains set until the user reads the register. for the bed, bcof, and becof bits, they are cleared when read and are not set again until the event has occurred again. for rlos, ra0, and ra1 bits, they are cleared when read if the condition no longer persists. status register (address = 4h) (msb) (lsb) ? ra1 ra0 bed becof bcof rlos s ync symbol description ? not assigned. could be any value. ra1 receive all 1?s. set when 40 consecutive 1?s are received in pseudorandom mode. allowed to be cleared when a 0 is received. ra0 receive all 0?s. set when 40 consecutive 0s are received in pseudorandom mode. allowed to be cleared when a 1 is received. bed bit error detection. set when bit error count is non - zero. cleared when read. becof bit error count overflow. set when the bit error counter overflows. cleared when read. bcof bit coun ter overflow. set when the bit counter overflows. cleared when read. rlos receive loss of sync. set when the receiver is searching for synchronization. remains set until read once sync is achieved. this bit is latched. sync sync. real - time status of the synchronizer. this bit is not latched. 3.2 pseudorandom pattern registers note: bit 1 of control register 4 determines if the addresses point to the tap select or seed registers. the tap select register is used to select the length and tap positions f or pseudorandom generation/reception. each bit that is set to a 1 denotes a tap at that location for the feedback path. the highest bit location set to a 1 is the length of the shift register. all pattern lengths are available in bit mode, patterns 2 4 - 1 and greater are available in nibble mode, and patterns 2 8 - 1 and greater are available in byte mode. the pattern generator generates all 1?s if the exponent in the polynomial is less than 4 (nibble mode) or 8 (byte mode). for example, to transmit/receive 2 15 - 1 (o.151) bit14 and bit13 would be set to a 1. all other bits would be 0. table 5 gives tap select and seed values for many pseudorandom patterns. the seed value is loaded into the transmit shift register on the rising edge of tl (cr1.0). tap sele ct/seed value registers (address = 5h ? 8h) (msb) (lsb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24
ds2174 16 of 24 table 3 - 3. pseudorandom pattern generation pattern type tap0 tap1 tap2 tap3 seed0/1/2/3 tinv rinv 2 3 - 1 (notes 1 and 2) 05 00 00 00 ff 0 0 2 4 - 1 (note 1) 09 00 00 00 ff 0 0 2 5 - 1 (note 1) 12 00 00 00 ff 0 0 2 6 - 1 (note 1) 30 00 00 00 ff 0 0 2 7 - 1 fracti onal t1 lb activate (note 1) 48 00 00 00 ff 0 0 2 7 - 1 fractional t1 lb deactivate (note 1) 48 00 00 00 ff 1 1 2 7 - 1 (note 1) 41 00 00 00 ff 0 0 2 8 - 1 maximal length b8 00 00 00 ff 0 0 2 9 - 1 o.153 (511 type) 10 01 00 00 ff 0 0 2 10 - 1 40 02 00 00 f f 0 0 2 11 - 1 o.152 and o.153 (2047 type) 00 05 00 00 ff 0 0 2 12 - 1 maximal length 29 08 00 00 ff 0 0 2 13 - 1 maximal length 0d 10 00 00 ff 0 0 2 14 - 1 maximal length 15 20 00 00 ff 0 0 2 15 - 1 o.151 00 60 00 00 ff 1 1 2 16 - 1 maximal length 08 d0 0 0 00 ff 0 0 2 17 - 1 04 00 01 00 ff 0 0 2 18 - 1 40 00 02 00 ff 0 0 2 19 - 1 maximal length 23 00 04 00 ff 0 0 2 20 - 1 o.153 04 00 08 00 ff 0 0 2 20 - 1 o.151 qrss (cr1.3 = 1) 00 00 09 00 ff 0 0 2 21 - 1 02 00 10 00 ff 0 0 2 22 - 1 01 00 20 00 ff 0 0 2 23 - 1 o.151 00 00 42 00 ff 1 1 2 24 - 1 maximal length 00 00 e1 00 ff 0 0 2 25 - 1 04 00 00 01 ff 0 0 2 26 - 1 maximal length 23 00 00 02 ff 0 0 2 27 - 1 maximal length 13 00 00 04 ff 0 0 2 28 - 1 04 00 00 08 ff 0 0 2 29 - 1 02 00 00 10 ff 0 0 2 30 - 1 maxi mal length 29 00 00 20 ff 0 0 2 31 - 1 04 00 00 40 ff 0 0 2 32 - 1 maximal length 03 00 20 80 ff 0 0 notes: 1) these pattern types do not work in byte mode. 2) these pattern types do not work in nibble mode.
ds2174 17 of 24 3.3 test register test register used for factory t est. all bits must be set to 0 for proper operation. test register (address = 9h) (msb) (lsb) test test test test test test test test symbol description test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. test factory use. must be set to 0 for proper operation. 3.4 count registers note : bit 2 of control register 4 determines if the addresses point to the bit count or error count registers. the b it count registers comprise a 48 - bit count of bits (actually rclk cycles) received at rdat. c47 is the msb of the 48 - bit count. the bit counter increments for each cycle of rclk when rclk_en is high. the bit counter is enabled regardless of synchronization . the status register bit bcof is set when this 48 - bit register overflows. the counter rolls over upon an overflow condition. the ds2174 latches the bit count into the bit count registers and clears the internal bit count when the lc bit in control registe r 1 is toggled from low to high. the error count registers comprise a 48 - bit count of bits received in error at rdat. the bit error counter is disabled during loss of sync. c47 is the msb of the 48 - bit count. the status register bit becof is set when this 48 - bit register overflows. the counter rolls over upon an overflow condition. the ds2174 latches the bit count into the bit error count registers and clears the internal bit error count when the lc bit in control register 1 is toggled from low to high. t he bit count and bit error count registers are used by an external processor to compute the ber performance on a loop or channel basis. count registers (address = ah ? fh) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 c15 c14 c13 c12 c11 c10 c9 c8 c23 c22 c 21 c20 c19 c18 c17 c16 c31 c30 c29 c28 c27 c26 c25 c24 c39 c38 c37 c36 c35 c34 c33 c32 c47 c46 c45 c44 c43 c42 c41 c40
ds2174 18 of 24 4. ram access 4.1 indirect addressing 512 bytes of memory, which is address ed indirectly, are available for repetitive patterns. da ta bytes are loaded one at a time into the indirect address register at address 0fh. the ram mode control bit, cr4.3, determines the access to the ram. if cr4.3 = 0, the ram is under control of the bert state machine. if cr4.3 = 1, the ram is under the con trol of the parallel port. this section discusses cr4.3 = 1. the accompanying flow chart describes the algorithm used to write repetitive patterns to the ram. the programmer initializes a counter (n) to - 1 in software, then sets cr4.3 and clears cr4.4. th e rising edge of cr4.3 resets the ram address pointer to address 00h. address 0fh becomes the indirect access port to the ram. a write cycle on the parallel port to address 0fh writes to the address in ram pointed to by the address pointer. the end of the write cycle, rising edge of wr, increments the address pointer. the programmer then increments the counter (n) by 1 and loops until the pattern load is complete. clear cr4.3 to return control of the ram to the bert state machine. finally, write the value i n the counter (n) back to address 04h and 05h to mark the last address of the pattern in memory. the ram contents can be verified by executing the same algorithm, replacing the parallel - port write with a read, and setting cr4.4. cr4.3 must remain set for the entire algorithm to properly increment the address pointer. yes write n to cr3 last byte? done cr4.3=1 cr4.4=0 n = - 1 write byte to address 0fh cr4.3 = 0 n = n + 1 start no if n > 255, then set cr4.0
ds2174 19 of 24 5. dc operation absolute maximum ratings* voltage range on any pin relative to ground - 1.0v to +5.5v operating temperature range for DS2174Qn - 40 o c to +85 o c storage temperature ran ge - 55 o c to +125 o c soldering temperature range see ipc/jedec j - std - 020a *this a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. table 5 - 1. recommended dc operating conditions (0c to +70c for DS2174Q; - 40c to +85c for DS2174Qn) parameter symbol min typ max units note s logic 1 v ih 2.2 5.5 v logic 0 v il - 0.3 +0.8 v supply voltage v dd 3.0 3.3 3.6 v table 5 - 2. dc characteristics (0 c to +70c for DS2174Q; v dd = 3.0v to 3.6v; - 40c to +85c for DS2174Qn; v dd = 3.0v to 3.6v) parameter symbol min typ max units not es supply current i dd 50 60 ma 1 lead capacitance c io 7 pf input leakage i il - 10 +10 a 2 input leakage (with pullups) i ilp - 500 +500 a 2 output leakage i lo - 10 +10 a 3 output current at 2.4v i oh - 4.0 ma output current at 2.4v i oh8 - 8.0 ma 4 output current at 0.4v i ol +4.0 ma output current at 0.4v i ol8 +8.0 ma 4 notes: 1) tclk = rclk = 155mhz serial mode; outputs open - circuited or 80mhz byte mode. 2) 0 v < v in < v dd . 3) applies to tdat when tristated. 4) applies to tdat[0] and tclko.
ds2174 20 of 24 6. ac timing characteristics 6.1 parallel port figure 6 - 1. read timing table 6 - 1. parallel port read timing ( 0c to +70c for DS2174Q; v dd = 3.0v to 3.6v; - 40c to +85c for DS2174Qn; v dd = 3.0v to 3.6v ) parameter symbol min typ max units notes cs setup time before rd t su(1) 5.0 ns a(3:0) setup time before rd t su(2) 10.0 ns a(3:0) hold time after rd - t h(1) 10.0 ns rd pulse width t pw 38 ns data output delay after rd t od 8.0 ns 1 data float time after rd - t f 2.0 ns 1 cs hold time after rd - t h(3) 5.0 ns - = rising edge = falling edge notes: 1) 50pf load. valid data t od a[3:0] cs rd d[7:0] data out t su(1) t su (2) t pw t h(1) t h(3) t f
ds2174 21 of 24 figure 6 - 2. write timing table 6 - 2. parallel port write timing (0c to +70c for DS2174Q; v dd = 3.0v to 3.6v; - 40c to +85 c for DS2174Qn; v dd = 3.0v to 3.6v) parameter symbol min typ max units notes cs setup time before wr t su(1) 5.0 ns a(3:0) setup time before wr t su(2) 10.0 ns a(3:0) hold time after wr - t h(1) 10.0 ns wr pulse width t pw 38 ns data setup time before wr - t s u(3) 10.0 ns data hold time after wr - t h(2) 5.0 ns cs hold time after wr - t h(3) 5.0 ns valid data t su(3) a[3:0] cs wr d[7:0] data in t su(1) t su (2) t pw t h(1) t h(3) t h(2)
ds2174 22 of 24 6.2 data interface figure 6 - 3 . transmit interface timing table 6 - 3. transmit data timing (0 c to +70c for DS2174Q; v dd = 3.0v to 3.6v; - 40c to +85c for DS2174Qn; v dd = 3.0v to 3.6v) parameter symbol min typ max units notes tclk clock period (nibble/byte mode) t cyc 12.5 ns tclk high time (nibble/byte mode) t pwh 5.0 ? t cyc ns tclk low time (nibble/byte mode) t pwl 5.0 ? t cyc ns tclk clock period (bit mode) t cyc 6.45 ns tclk high time (bit mode) t pwh 2.0 ? t cyc ns 3 tclk low time (bit mode) t pwl 2.0 ? t cyc ns 3 tclk_en setup time before tclk - t su 2.5 ns tclk_en hold time after tclk - t h 2.5 ns tclko output delay af ter tclk - t od 6.0 ns 1 tclko high time (nibble/byte mode) t pwh(1) 5.0 ns 1 tclko high time (bit mode) t pwh(1) 2.0 ns 1 tdat output delay after tclko t od(1) 5.0 ns 1, 2 notes: 1) 20pf load. 2) tdat follows falling edge of tclko if cr4.5 = 0, rising edge if cr4.5 = 1. 3) guaranteed by design. tclk tdat tclko tclk_en t cyc t pwh t pwl t h t su t pwh(1) t od t od(1) gapped clock gapped clock data out
ds2174 23 of 24 figure 6 - 4. receive interface timing table 6 - 4. receive data timing (0c to +70 c for DS2174Q; v dd = 3.0v to 3.6v; - 40c to +85c for DS2174Qn; v dd = 3.0v to 3.6v) parameter symbol min typ max units notes rclk clock period (nibble/byte mode) t cyc 12.5 ns rclk high time (nibble/byte mode) t pwh 5.0 ? t cyc ns rclk low time (nibble/byte mode) t pwl 5.0 ? t cyc ns rclk clock period (bit mode) t cyc 6.45 ns rclk high time (bit mode) t pwh 2.0 ? t cyc ns 1 rclk low time (bit mode) t pwl 2.0 ? t cyc ns 1 rclk_en setup time before rclk - t su(1) 2.5 ns rclk_en hold time after rclk - t h(1) 2.5 ns rdat(7:0) setup time before rclk - t su(2) 2.5 ns rdat(7:0) hold time after rclk - t h(2) 2.5 ns notes : 1) guaranteed by design. t cyc t pwh t pwl t su(2) t h(2) t su(1) t h(1) rclk rdat rclk_en ignore ignore ignore
ds2174 24 of 24 7. mechanical dimensions

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